Efficient Detailed Routing for FPGA Back-End Flow Using Reinforcement Learning

Over the past few years, computation capability of field-programmable gate arrays (FPGAs) has increased tremendously. This led to increase in complexity designs implemented on FPGAs and time taken by FPGA back-end flow. The flow comprises many steps, routing is one most critical steps among them. Routing normally constitutes more than 50% total an optimization at this step can lead overall In work, we propose enhancements incorporating a reinforcement learning (RL)-based framework. proposed RL-based framework, use ?-greedy approach customized reward functions speed up while maintaining similar or better quality results (QoR) as compared conventional negotiation-based congestion-driven solution. For experimentation, two sets widely deployed, large heterogeneous benchmarks. Our show that, for greedy combined with modified function gives purely exploratory approaches. Moreover, incorporation framework its comparison algorithm shows that enhancement requires less giving QoR. On average, speedup 35% recorded solutions. Finally, leads reduction execution 25%.